In CMOS technologies, NFET and PFET devices are optimized to achieve required design performance. This optimization can include doping concentrations, material selections and dimensions. For example, in conventional CMOS technologies, and particularly in dual EPI process schemes for source and drain formation, both the NFET and PEET devices share many of the same processes and topology to reduce manufacturing costs and provide optimal performance, where possible. However, in current process schemes, and in particular dual EPI process schemes, the spacer thickness of the NFET and PFET devices are different, with the NFET device having a thicker spacer than the PFET devices. This thicker spacer leads to degraded device performance due to longer proximity to the channel.